Progress
Following on from DigiLite-ZL project running the DigiLite-UK configuration, this page details progess with the FPGA aspect of the project.
Phase two of the project has been to implement the DVB-S encoder and serialialiser using the DE0-nano FPGA board. This allows a significant simplification of the associated software architecture since plain ordinary Transport Stream can be carried over the USB interface. This then allow the system to become somewhat operating system agnostic.
Congratulations
Ben Gelb, N1VF has woven his magic, and pretty much hit the target of getting the FPGA implemnetation running first go. This version is running at 4M sym/sec and has been left spooling looped TS data for several hours without a hiccup. Current implementation occupies about 4% system resources of the Altera EP4CE22F17C6 FPGA.
Development was done using the free Altera Quartus II development environment, and the DE0-nano was purchased from Digikey for around US$79.
Forwards
Ben has made the source for the FPGA available here.
Comments and corrections always welcome.
Regards,
26 Oct 2011, New Zealand
